As microelectronic devices continue to scale, the contact resistance of typical doped source drain structures increases as the contact dimension is reduced. At the same time, the channel resistance keeps reducing as channel lengths scale down. The result is that a proportionally larger voltage drop is induced in the parasitic source/drain regions leading to diminished improvement in device performance. There is a need to reduce the source/drain parasitic resistance, since it is rapidly becoming a bottleneck for device performance.